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hm51w17805 series 16 m edo dram (2-mword 8-bit) 2 k refresh ade-203-631d (z) rev. 4.0 nov. 1997 description the hitachi hm51w17805 is a cmos dynamic ram organized 2,097,152-word 8-bit. it employs the most advanced cmos technology for high performance and low power. the hm51w17805 offers extended data out (edo) page mode as a high speed access mode. multiplexed address input permits the hm51w17805 to be packaged in standard 28-pin plastic soj and 28-pin tsop. features single 3.3 v ( 0.3 v) access time: 50 ns/60 ns/70 ns (max) power dissipation ? active mode: 396 mw/360 mw/324 mw (max) ? standby mode : 7.2 mw (max) : 0.54 mw (max) (l-version) edo page mode capability long refresh period ? 2048 refresh cycles : 32 ms : 128 ms (l-version) 4 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh ? self refresh (l-version) battery backup operation (l-version)
hm51w17805 series 2 ordering information type no. access time package hm51w17805j-5 hm51w17805j-6 hm51w17805j-7 50 ns 60 ns 70 ns 400-mil 28-pin plastic soj (cp-28da) hm51w17805lj-5 hm51w17805lj -6 hm51w17805lj -7 50 ns 60 ns 70 ns hm51w17805s-5 hm51w17805s-6 hm51w17805s-7 50 ns 60 ns 70 ns 300-mil 28-pin plastic soj (cp-28dna) hm51w17805ls-5 hm51w17805ls-6 hm51w17805ls-7 50 ns 60 ns 70 ns hm51w17805tt-5 hm51w17805tt-6 hm51w17805tt-7 50 ns 60 ns 70 ns 400-mil 28-pin plastic tsop ii (ttp-28da) hm51w17805ltt-5 hm51w17805ltt-6 hm51w17805ltt-7 50 ns 60 ns 70 ns hm51w17805ts-5 hm51w17805ts-6 hm51w17805ts-7 50 ns 60 ns 70 ns 300-mil 28-pin plastic tsop ii (ttp-28db) hm51w17805lts-5 hm51w17805lts-6 hm51w17805lts-7 50 ns 60 ns 70 ns
hm51w17805 series 3 pin arrangement 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v cc i/o0 i/o1 i/o2 i/o3 we ras nc a10 a0 a1 a2 a3 v cc v i/o7 i/o6 i/o5 i/o4 cas oe a9 a8 a7 a6 a5 a4 v ss ss (top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v cc i/o0 i/o1 i/o2 i/o3 we ras nc a10 a0 a1 a2 a3 v cc v i/o7 i/o6 i/o5 i/o4 cas oe a9 a8 a7 a6 a5 a4 v ss ss hm51w17805ts/lts series (top view) hm51w17805s/ls series hm51w17805tt/ltt series hm51w17805j/lj series pin description pin name function a0 to a10 address input row/refresh address a0 to a10 column address a0 to a9 i/o0 to i/o7 data input/data output ras row address strobe cas column address strobe we read/write enable oe output enable v cc power supply v ss ground nc no connection
hm51w17805 series 4 block diagram ? ? ? ? ? ? a0 a1 to a9 timing and control column address buffers row address buffers i/o buffers i/o0 to i/o7 ras cas we oe column decoder row decoder 2m array 2m array 2m array 2m array 2m array 2m array 2m array 2m array a10
hm51w17805 series 5 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C0.5 to v cc + 0.5 ( 4.6 v (max)) v supply voltage relative to v ss v cc C0.5 to +4.6 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit note supply voltage v cc 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il C0.3 0.8 v 1 note: 1. all voltage referred to v ss .
hm51w17805 series 6 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) -5 -6 -7 parameter symbol min max min max min max unit test conditions operating current *1, *2 i cc1 110 100 90 ma t rc = min standby current i cc2 2 2 2 ma ttl interface ras , cas = v ih dout = high-z 1 1 1 ma cmos interface ras , cas 3 v cc C 0.2v dout = high-z standby current (l-version) i cc2 150 150 150 m a cmos interface ras , cas 3 v cc C 0.2v dout = high-z ras -only refresh current *2 i cc3 110 100 90 ma t rc = min standby current *1 i cc5 5 5 5 ma ras = v ih , cas = v il dout = enable cas -before- ras refresh current i cc6 110 100 90 ma t rc = min edo page mode current *1, *3 i cc7 100 90 85 ma t hpc = min battery backup current *4 (standby with cbr refresh) (l-version) i cc10 400 400 400 m a cmos interface dout = high-z cbr refresh: t rc = 62.5 m s t ras 0.3 m s self refresh mode current (l-version) i cc11 250 250 250 m a cmos interface ras , cas 0.2v dout = high-z input leakage current i li C10 10 C10 10 C10 10 m a 0 v vin 4.6 v output leakage current i lo C10 10 C10 10 C10 10 m a 0 v vout 4.6 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc 2.4 v cc v high iout = C2 ma output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . 4. cas = l ( 0.2 v) while ras = l ( 0.2 v).
hm51w17805 series 7 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol typ max unit notes input capacitance (address) c i1 5 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-in, data-out) c i/o 7 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout. ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) *1, *2, *18 test conditions input rise and fall time: 2 ns input levels: v il = 0 v, v ih = 3 v input timing reference levels: 0.8 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v output load: 1 ttl gate + c l (100 pf) (including scope and jig)
hm51w17805 series 8 read, write, read-modify-write and refresh cycles (common parameters) hm51w17805 -5 -6 -7 parameter symbol min max min max min max unit notes random read or write cycle time t rc 84 104 124 ns ras precharge time t rp 30 40 50 ns cas precharge time t cp 81013ns ras pulse width t ras 50 10000 60 10000 70 10000 ns cas pulse width t cas 8 10000 10 10000 13 10000 ns row address setup time t asr 000ns row address hold time t rah 81010ns column address setup time t asc 000ns column address hold time t cah 81013ns ras to cas delay time t rcd 12 37 14 45 14 52 ns 3 ras to column address delay time t rad 10 25 12 30 12 35 ns 4 ras hold time t rsh 10 13 13 ns cas hold time t csh 35 40 45 ns cas to ras precharge time t crp 555ns oe to din delay time t oed 13 15 18 ns 5 oe delay time from din t dzo 000ns6 cas delay time from din t dzc 000ns6 transition time (rise and fall) t t 250250250ns7
hm51w17805 series 9 read cycle hm51w17805 -5 -6 -7 parameter symbol min max min max min max unit notes access time from ras t rac 50 60 70 ns 8, 9 access time from cas t cac 13 15 18 ns 9, 10, 17 access time from address t aa 25 30 35 ns 9, 11, 17 access time from oe t oea 131518ns 9 read command setup time t rcs 000ns read command hold time to cas t rch 000ns12 read command hold time from ras t rchr 50 60 70 ns read command hold time to ras t rrh 000ns12 column address to ras lead time t ral 25 30 35 ns column address to cas lead time t cal 15 18 23 ns cas to output in low-z t clz 000ns output data hold time t oh 333ns20 output data hold time from oe t oho 333ns output buffer turn-off time t off 13 15 15 ns 13, 20 output buffer turn-off to oe t oez 131515ns 13 cas to din delay time t cdd 13 15 18 ns 5 output data hold time from ras t ohr 333ns20 output buffer turn-off to ras t ofr 131515ns 20 output buffer turn-off to we t wez 131515ns we to din delay time t wed 13 15 18 ns ras to din delay time t rdd 13 15 18 ns ras next cas delay time t rncd 50 60 70 ns
hm51w17805 series 10 write cycle hm51w17805 -5 -6 -7 parameter symbol min max min max min max unit notes write command setup time t wcs 000ns14 write command hold time t wch 8 10 13 ns write command pulse width t wp 8 10 10 ns write command to ras lead time t rwl 8 10 13 ns write command to cas lead time t cwl 8 10 13 ns data-in setup time t ds 000ns15 data-in hold time t dh 8 10 13 ns 15 read-modify-write cycle hm51w17805 -5 -6 -7 parameter symbol min max min max min max unit notes read-modify-write cycle time t rwc 111 135 161 ns ras to we delay time t rwd 67 79 92 ns 14 cas to we delay time t cwd 30 34 40 ns 14 column address to we delay time t awd 42 49 57 ns 14 oe hold time from we t oeh 13 15 18 ns refresh cycle hm51w17805 -5 -6 -7 parameter symbol min max min max min max unit notes cas setup time (cbr refresh cycle) t csr 555ns cas hold time (cbr refresh cycle) t chr 8 10 10 ns we setup time (cbr refresh cycle) t wrp 000ns we hold time (cbr refresh cycle) t wrh 8 10 10 ns ras precharge to cas hold time t rpc 555ns
hm51w17805 series 11 edo page mode cycle hm51w17805 -5 -6 -7 parameter symbol min max min max min max unit notes edo page mode cycle time t hpc 20 25 30 ns 19 edo page mode ras pulse width t rasp 100000 100000 100000 ns 16 access time from cas precharge t cpa 30 35 40 ns 9, 17 ras hold time from cas precharge t cprh 30 35 40 ns output data hold time from cas low t doh 3 3 3 ns 9, 17 cas hold time referred oe t col 8 10 13 ns cas to oe setup time t cop 5 5 5 ns read command hold time from cas precharge t rchc 30 35 40 ns edo page mode read-modify-write cycle hm51w17805 -5 -6 -7 parameter symbol min max min max min max unit notes edo page mode read- modify-write cycle time t hprwc 57 68 79 ns we delay time from cas precharge t cpw 45 54 62 ns 14 refresh parameter symbol max unit note refresh period t ref 32 ms 2048 cycles refresh period (l-version) t ref 128 ms 2048 cycles
hm51w17805 series 12 self refresh mode (l-version) hm51w17805l -5 -6 -7 parameter symbol min max min max min max unit notes ras pulse width (self refresh) t rass 100 100 100 m s ras precharge time (self refresh) t rps 90 110 130 ns cas hold time (self refresh) t chs C50 C50 C50 ns notes: 1. ac measurements assume t t = 2 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles are required. 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl loads and 100 pf. 10. assumes that t rcd 3 t rcd (max) and t rad t rad (max). 11. assumes that t rcd t rcd (max) and t rad 3 t rad (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. these parameters are referred to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. 16. t rasp defines ras pulse width in edo page mode cycles. 17. access time is determined by the longest among t aa , t cac and t cpa . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 19. t hpc (min) can be achieved during a series of edo page mode write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle (t cas + t cp + 2 t t ) becomes greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2).
hm51w17805 series 13 20. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off . 21. please do not use t rass timing, 10 m s t rass 100 m s. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass 3 100 m s, then ras precharge time should use t rps instead of t rp . 22. if you use ras only refresh or cbr burst refresh mode in normal read/write cycles, 2048 cycles of distributed cbr refresh with 15.6 m s interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 23. if you use distributed cbr refresh mode with 15.6 m s interval in normal read/write cycle, cbr refresh should be executed within 15.6 m s immediately after exiting from and before entering into self refresh mode. 24. repetitive self refresh mode without refreshing all memory is not allowed. once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hm51w17805 series 14 timing waveforms *25 read cycle ras address we dout oe din t rc t ras t rp t csh t crp t rcd t rsh t cas t t t rad t ral t cal t asc t cah t asr row column t rah t rcs t rch t rrh t cdd t dzc high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez cas t rdd t wed t ofr t ohr t wez t rchr early write cycle
hm51w17805 series 15 ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t cas
hm51w17805 series 16 delayed write cycle *18 address cas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t oed t oeh t clz t oez high-z din high-z invalid dout read-modify-write cycle *18
hm51w17805 series 17 address ras din dout oe we t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t oed t oeh t oea t cac t aa t rac t oho t oez t clz dout high-z cas
hm51w17805 series 18 ras -only refresh cycle ras cas address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off t ofr
hm51w17805 series 19 cas -before- ras refresh cycle ras cas we dout address t rc t rp t ras t rpc t csr t chr t rpc t crp t cp t wrh t wrp t cp t t t off t ofr high-z t rp
hm51w17805 series 20 hidden refresh cycle din oe dout we address ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rcd t rsh t chr t crp t rad t ral t cah t asc t rah t asr t t cdd t dzc dzo t oed t oez t oho t off t oh t cac t aa t rac t clz t dout column row oea t high-z t rch t rrh cas t wed t rdd wez t ofr t ohr t rcs t wrh t rrh t wrp t wrh t wrp edo page mode read cycle
hm51w17805 series 21 din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t cac t cpa t t oez t oea t oez t aa t cac t t rasp cop t rp t cas t cas t cas t cal t csh t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 2 dout 4 dout 1 t cas t rcs t t rcs dout 3 t oho t t cprh t hpc t oea t wez dzo t oed t rncd oho doh rch t rchr t cal t cal t cal t rsh t rchc cpa asc
hm51w17805 series 22 edo page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n cas
hm51w17805 series 23 edo page mode delayed write cycle *18 we din oe dout address ras t rasp t rp t crp t rsh t cas t hpc t cas t cas t csh t rcd t t t cp t cp t asc t cah t asc t cah t asc t cah t rad t asr t rah t rcs t rcs t rcs t rwl t cwl t cwl t cwl t wp t wp t wp t dzc t ds t dzc t ds t ds t dzc t dh t dh t dh t dzo t oed t dzo t oed t dzo t oed t oeh t oeh t oeh t oez t clz t clz t oez t clz t oez invalid dout invalid dout invalid dout din 1 din 2 din n column n column 2 column 1 row high-z cas
hm51w17805 series 24 edo page mode read-modify-write cycle *18 we din oe dout address ras t rasp t crp t cp t hprwc t t t rcd t cas t cp t cas t cas t rad t asr t asc t asc t asc t rah t cah t cah t cah t cwl t cpw t cwl t cpw t cwl t rwd t awd t awd t awd t cwd t rcs t cwd t rcs t cwd t rcs t wp t wp t wp t ds t dzc t ds t dzc t ds t dzc t dh t dh t dh t dzo t dzo t dzo t oeh t oeh t oeh t aa t rac t oez t clz dout n dout 2 dout 1 din 1 din 2 din n column n column 2 column 1 t rp row t rwl t oho t oea t cac t oez t clz t oho t oea t cac t cpa t oez t clz t oho t oea t cac t cpa high-z t oed t oed t oed aa t aa t t rsh cas
hm51w17805 series 25 edo page mode mix cycle (1) din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t cpa t oez t aa t oea t t rasp t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal row dout 2 dout 4 cpa t cas t wcs dout 3 t t t wp t wch t wed t wez t ds t dh t ds t dh din 3 din 1 t oea t oed t cac t asc t cpw t awd oho t cal t cal t cal t rcs t rcs t csh t rcd t rsh doh asc t
hm51w17805 series 26 edo page mode mix cycle (2) din oe dout we address ras cas t cp t rncd t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t oez t t oea t t rasp t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t rcs row dout 1 dout 4 cpa t cas dout 3 t oho t wed t wez t ds t dh t ds t din 3 din 2 t oea t t cac t cpw t rch t rcs t wch t rac t oed t col t oea t oho t oez t dh oed t rcs t cal t cal t cal t cal t rcd t rchr t wcs t rsh t wp t asc aa cop
hm51w17805 series 27 self refresh cycle (l-version)* 21, 22, 23, 24 ras dout t rp t rass t rps t rpc t t t cp t csr t chs t crp t off t ofr high-z cas wrp t wrh t we
hm51w17805 series 28 package dimensions hm51w17805j/lj series (cp-28da) 9.40 0.25 1 14 0.43 0.10 3.50 0.26 15 28 18.54 max 18.17 0.74 10.16 0.13 11.18 0.13 0.10 2.85 0.12 1.30 max 1.27 0.80 +0.25 ?.17 hitachi code jedec eiaj weight (reference value) cp-28da conforms conforms 1.16 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension
hm51w17805 series 29 hm51w17805s/ls series (cp-28dna) 0.43 0.10 3.50 0.26 1.165 max 0.10 1.27 hitachi code jedec eiaj weight (reference value) cp-28dna 0.95 g 0.41 0.08 unit: mm 15 28 1 14 6.79 0.18 + 0.25 ?0.36 2.45 0.74 18.84 max 18.41 7.62 0.12 8.51 0.12 0.90 0.26 dimension including the plating thickness base material dimension
hm51w17805 series 30 hm51w17805tt/ltt series (ttp-28da) 1.27 0.21 m 0.42 0.08 0.10 10.16 18.41 18.81 max 15 14 28 1 1.20 max 0 ?5 0.13 0.05 11.76 0.20 0.50 0.10 1.15 max 0.145 0.05 0.68 0.80 hitachi code jedec eiaj weight (reference value) ttp-28da conforms ? 0.43 g 0.40 0.06 0.125 0.04 unit: mm dimension including the plating thickness base material dimension
hm51w17805 series 31 hm51w17805ts/lts series (ttp-28db) hitachi code jedec eiaj weight (reference value) ttp-28db ? ? 0.35 g 18.41 18.81 max 114 28 15 1.27 0.21 0.42 0.08 1.20 max 0.10 7.62 9.22 0.2 0.13 0.05 0 ?5 m 1.15 max 0.50 0.10 0.63 0.145 0.05 0.40 0.06 0.125 0.04 0.80 unit: mm dimension including the plating thickness base material dimension
hm51w17805 series 32 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm51w17805 series 33 revision record rev. date contents of modification drawn by approved by 1.0 oct. 1, 1996 initial issue y. kasama m. mishima 2.0 nov. 12, 1996 addition of hm51w17805-5 series addition of hm51w17805s/ls series (cp-28dna) addition of hm51w17805ts/lts series (ttp-28db) power dissipation (active) 432/396 mw(max) to 396/360/324 mw (max) dc characteristics i cc1 max: 120/110 ma to 110/100/90 ma i cc3 max: 120/110 ma to 110/100/90 ma i cc6 max: 120/110 ma to 110/100/90 ma i cc7 max: 120/110 ma to 100/90/85 ma ac characteristics t rcd min: 20/20 ns to 12/14/14 ns t rad min: 15/15 ns to 10/12/12 ns t rsh min: 15/18 ns to 10/13/13 ns t rrh min: 0/0 ns to 5/5/5 ns t rwc min: 149/175 ns to 111/135/161 ns t rwd min: 82/95 ns to 67/79/92 ns t cwd min: 37/43 ns to 30/34/40 ns t awd min: 52/60 ns to 42/49/57 ns t rpc min: 0/0 ns to 5/5/5 ns t hprwc min: 79/90 ns to 57/68/79 ns timing waveforms addition of t rncd timing to edo page mode mix cycle (2) y. kasama y. matsuno 3.0 feb. 25, 1997 ac characteristics t rrh min: 5/5/5 ns to 0/0/0 ns y. kasama y. matsuno 4.0 nov. 1997 change of subtitle

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